WHO WE ARE
Committed to Excellence
Yinon Levy: Phy & VLSI Design Manager
System definition for 5G New Radio Base Station, Architecture, RTL design & Verification of Transmitter and Receiver for mobile wireless modem 5G New Radio based on OFDMA technology. Modules include LDPC Decoder/Encoder, Channel Estimator, Rate De Rate Matching, Data Detection, Beam Selection, Decimator and Interpolator involving with all TX/RX modem chain. Implementation done on FPGA, Xilinx Zync UltraScale+ MPSoC.
Design algorithms for Interpolator, Decimator and DDS using MATLAB models and implement these models via RTL design.
Architecture definition and RTL design of LDPC FEC(Forward Error Correction) Decoder , BCH FEC Decoder and DAGC for DOCSIS 3.1 (Data Over Cable Service Interface Specifications).
Define and lead the architecture design of 4G wireless communication chips. Define the system performance of the 4G mobile modem receiver. Implement the 4G modem mobile via FPGA's.RTL design of most of the Receiver: FIR, Resampler, FFT, DAGC, Ranging, APC, CINR, Channel Quality Indicator, Channel estimator, RX Beam Forming, Up-link Sounding, PRACH(LTE), PUCCH(LTE), MMSE(LTE). Architecture and design the ASS (Arm Sub System) for WIMAX UT (User Terminal) ASIC for Samsung.
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Design Two ASIC for ECI: Architecture plus full RTL design. ATM cell processors Vendors: NEC, Infineon.
Design SONET/SDH system level Generator and Analyzer in VHDL.
Yinon holds a B.Sc. in Electrical Engineering
from the Technion in Haifa and
a MBA from the Tel-Aviv University.
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Meir Rivlin: Phy & VLSI Designer
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Design Ethernet Layers marker, Algorithms of binary search, AES, FFT, IIR and RS
RTL design & Verification of Transmitter and Receiver for mobile wireless modem 5G New Radio based on OFDMA technology. Design RTL Compression communication algorithm
and PCI adaptor
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Design RTL CoDesign Verification scripts for running automatic test cases.
Meir holds a B.Sc. in Electrical Engineering
from Ben Gurion University
a MBA from the British Heriot-watt University.
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